1. Field of the Invention
The present invention relates generally to a dynamic memory device and a driving method therefor. More specifically, the invention relates to a dynamic memory device having a self-refreshing function and a driving method therefor.
2. Description of the Related Art
In a dynamic memory device having a self-refreshing (hereinafter referred to as "SR") function, after detection of CBR (CAS Before RAS) operation, when both of a row address control signal RAS* (* represents that low level is an active level, hereinafter "*" will be used to represent the same meaning), and a column address control signal CAS* are held in active (low) level, an operation mode is switched into a self-refreshing mode after expiration of a predetermined self-refreshing triggering period to automatically perform refreshing operation for a memory cell array at a predetermined refreshing period.
One example (first example) of the dynamic memory device having the self-refreshing function is illustrated in FIG. 7. The shown dynamic memory device includes a CBR operation detecting circuit 1x outputting a CBR entry signal CBRE which becomes active level by detecting active level of the column address control signal CAS* when the row address control signal RAS* is switched from inactive state (high level) into active level (low level) (CBR operation), and becomes inactive in response to switching of the row address control signal RAS* into inactive level, an oscillation circuit 2 for outputting a predetermined frequency of oscillation clock signal OCK in response to active level of the CBR entry signal CBRE, an SR entry timing signal generating portion 10 for outputting an SR entry timing signal SRET in response to a predetermined count value by counting the oscillation clock signal, an SR detection circuit 11 outputs an active level self-refreshing entry signal SRE when the CBR entry signal CBRE is active when the SR entry timing signal SRET is output, a refresh timing signal generating portion 3x becoming active in response to the active level of the self-refreshing entry signal SRE, counting the oscillation clock signal OCK for generating a predetermined period of self-refreshing entry signal RFTx, an SR control circuit 5 responsive to the active level of the self-refreshing entry signal SRE to output a self-refreshing control signal SRCX of a predetermined width in synchronism with the refreshing timing signal RFTx, to a refreshing control circuit 6x. An internal address generating portion 7 and a row address control circuit 8, after detecting the CBR operation, generate an internal address signal IAD sequentially updated address values in synchronism with the self-refreshing control signal SRCx when the self-refreshing entry signal SRE is active, the internal address signal IAD sequentially updated the address values in synchronism with the row address control signal RAS* of an external control signal when the self-refreshing entry signal SRE is inactive, selecting and outputting an external address signal EAD according to external control signal (RAS*, CAS*), and controlling refreshing operation and so forth of the memory cell array (not shown) when the CBR operation is not detected.
Next, refreshing operation of the dynamic memory device will be discussed in conjunction with the timing chart of the respective signal shown in FIG. 8.
The CBR operation detecting circuit 1x becomes active (high level) by detecting the CBR operation and generates the CBR entry signal CBRE becoming inactive (low level) when the row address control signal RAS* becomes inactive level (high level). In response to the active level of the CBR entry signal CBRE, the oscillation circuit 2 generates the oscillation clock signal OCK.
The SR entry timing signal generating portion 10 counts the oscillation clock signal OCK to output the SR entry timing signal SRET at the predetermined timing. The SR detection circuit 11 makes a judgement that the self-refreshing mode is to begin if the CBR entry signal CBRE is active at an output timing of the SR entry timing signal SRET, and outputs the active level self-refreshing entry signal SRE.
The refreshing timing signal generating portion 3x becomes active when the self-refreshing entry signal SRE becomes active to generate the predetermined period of refreshing timing signal RFTx by counting the oscillation clock signal OCK. The SR control circuit 5 outputs a predetermined period of the self-refreshing control signal SRCX in synchronism with the refreshing timing signal RFTx.
The refreshing control circuit 6x outputs a first refresh control signal RFC1 which becomes active level in response to variation of the row address control signal RAS* after detection of the CBR operation and inactive level in response to variation of the self-refreshing entry signal SRE into active level (or variation of one of the RAS* and the CAS* into inactive level, neglected from FIG. 8), and becomes active level in synchronism with the self-refreshing control signal SRCX when the self-refreshing entry signal SRE is active level and inactive level when the self-refreshing entry signal SRE is inactive, and a second refresh control signal RFC2 varying level variation similarly to the first refresh control signal, and in addition thereto, becomes active in synchronism with the active level of the row address control signal RAS*, for controlling the internal address generation circuit 7 and the row address control circuit 8.
The internal address generating portion 7 generates the internal address signal IAD sequentially updated address value in synchronism with the active level of the first refreshing control signal RFC1. The row address control circuit 8 selects the internal address signal IAD for synchronized with the first refreshing control signal RFC1 when the CBR operation is detected, according to first and second refreshing control signals RFC1 and RFC2, and selects the external address signal EAD in response to the active level of the row address control signal RAS* when the CBR operation is not detected. Namely, when the self-refreshing mode is executed, after detection of the CBR operation, CBR refreshing operation (once at the first time) is performed until the self-refreshing mode is detected (zone A shown in FIG. 8), and self-refreshing operation is performed after detection of the self-refreshing mode to perform refreshing by the internal address IAD in synchronism with the refreshing timing signal RFTx. If the CBR operation is detected but the self-refreshing mode is not detected, so called CBR refreshing operation is performed by the internal address signal IAD in synchronism with the row address control signal RAS*. When the CBR operation is not detected, normal refreshing operation is performed based in the external address signal EAD taken in synchronism with the row address control signal RAS*.
The self-refreshing mode in the dynamic memory device is frequently used when the power source is switched into a back-up power source and when the data holding condition becomes effected. It is thus desirable to make power consumption quite smaller even by prolonging the refreshing interval. Thus, in the foregoing dynamic memory device, in order to realize low power consumption, the refreshing interval of the self-refreshing mode is set long.
For example, in a 16 Mbit dynamic memory device, a refreshing interval in the normal operation is 32 ms. During this period, the refreshing cycle is 2048 (refreshing period about 16 .mu.m). In the self-refreshing mode, the refreshing interval is longer than 300 ms(hereinafter referred to as over 300 ms). The refresh period, namely, the period of RFTx, SRCx, is longer than or equal to 150 .mu.s (over 150 .mu.s).
In the above-mentioned dynamic memory device, due to tolerance or so forth in the production stage, a provision in a refreshing interval (e.g. 300 ms) in the low power consumption type self-refreshing mode is not satisfied in many cases. In such cases, such a memory device is commercialized as a product without a self-refreshing function. Namely, the yield of the product with the self-refreshing function is generally not high.
On the other hand, a data holding period of the memory cell is variable depending upon fluctuation in the production stage, and is significantly influenced by the use environment, and particularly on environmental temperature. In order to permit use in the worst use condition, it is typical to shorten a refreshing interval in the self-refreshing mode. In such case, power consumption is increased.
Therefore, depending upon fluctuation in production stage and upon use environment, there has been proposed the dynamic memory device which varies refreshing interval in the self-refreshing mode. (For example, see Japanese Unexamined Patent Publication (Kokai) No. 3-59876, in which is disclosed a storage holding mode instead of the self-refreshing mode).
Block diagram of the dynamic memory device (second example) and timing chart of signals of respective portion are shown in FIGS. 9 and 10.
The shown dynamic memory device includes a refreshing period generating circuit 21 generating refreshing timing signals RFTa and RFTb of mutually different periods, a timing detecting means 24 outputting a refreshing information set signal RFIS by detecting the column address control signal CAS* and a write control signal WE* in active level (low level) at a timing where the row address control signal RAS* switches from inactive level (high level) to active level (low level), storage means 25 reading out and storing the level ("1" or "0") of the data signal DI according to the refreshing information set signal RFIS), a selection circuit 22 for selecting one of the refreshing timing signals REFTa and RFTb according to the level of the signal (refresh information RFI) stored in storage means 25, a timing control circuit 26 generating various timing signals including the refreshing timing signal RFTn in normal operation according to the row address control signal RAS*, the column address control signal CAS* and a write control signal WE*, and a trigger signal selection curcuit 23 selecting the refresh timing signal RFTs selected by the selection means 22 when the external storage holding mode signal REF is the storage holding mode, and outputting a refreshing start-up signal RCE with selecting the refreshing timing signal RFTn during normal operation while not in the storage holding mode. The address of the row address signal is sequentially updated according to the refreshing start-up signal RCE to perform refreshing operation of the memory cell array.
In this dynamic memory device, since the refreshing period in the storage holding mode can be determined depending upon the use condition, such as environmental temperature upon refreshing operation, characteristics determined in the production stage and level of the input data signal DI in consideration of the power consumption, or the like. Therefore, the power consumption can be reduced depending upon the use environment and the like.
The above-mentioned conventional dynamic memory device in the first example encounters the problems of low production and low yield of production with the self-refreshing function when longer refreshing period is provided for low power consumption type since the refreshing interval at the self-refreshing mode is fixed at a constant value, amount of the product becomes smaller, on the contrary when shorter refreshing period is provided, though yield in the products with the self-refreshing function can be improved, power consumption is increased. On the other hand, in the second example, since the refreshing interval can be selected depending upon use environment or so forth, power consumption can be reduced and yield in production can be improved. However, four external signals DI, RAS*, CAS* and WE* are required for selecting the refreshing interval. Therefore, signal control becomes complicated. Also, the level of the external data signal is determined in consideration of the characteristics of the environmental temperature and upon production, power consumption and so forth. Thus, it is possible that errors on setting of level of the data signal occur, and cause erasure of the stored data.